Enabling the Rise of Advanced Packaging—NAURA Leads the Way

Amid AI's rapid advancement—from conversational agents to AI-generated images and short-form videos—the expanding landscape of real-world applications is now catalyzing both large-model development and semiconductor industry growth. The soaring demand for AI drives the need for high-performance chips capable of advanced computing, sensing, storage, communication, and security, unlocking vast innovation potential in integrated circuit technology.

In response, 3D integration technologies such as TSV are revolutionizing chip design, dramatically boosting performance and yield. High-bandwidth memory (HBM)^[1] and CoWoS^[2] packaging methods are now mainstream and accelerating, fueling high-quality development within the semiconductor equipment sector.

With over two decades of experience in semiconductor equipment, NAURA offers end-to-end solutions for advanced packaging. These cover TSV fabrication, front-side dual-damascene etching, back-side copper reveal etch, and RDL processes—across etch, thin film, furnace, and cleaning platforms, totaling more than 20 specialized tools.

NAURA's PSE V300 excels in TSV processes by combining rapid gas switching and RF power control, enabling precise profile control in deep silicon etching with ultra-high aspect ratios. It delivers damage-free sidewalls and line edges, superior etch uniformity, and enhanced selectivity. The tool adopts a single-wafer-per-chamber architecture, which ensures exceptional gas flow uniformity and profile circularity. Yield is further improved through optimized wafer edge protection design. For 2.5D applications^[3], NAURA provides customized etch solutions supporting both BVR (Backside Via Reveal) and BFR (Backside Flat Reveal) processes. The HSE D300, engineered for Plasma Dicing, offers high etch rates and aspect ratio capabilities tailored to small chip manufacturing. It supports multiple cooling schemes for UV tapes^[4], ensuring film stretchability and delivering high-quality chip singulation. The BMD P300, a flagship descum system for packaging, offers robust solutions for photoresist and metal residue removal, as well as surface activation across Bumping, Fan-out, and 2.5D/3D applications.

NAURA utilizes PEALD (Plasma Enhanced Atomic Layer Deposition) to deposit conformal silicon dioxide protective layers, achieving excellent sidewall coverage and bottom step coverage. In TSV Barrier/Seed Layer Deposition, its PVD systems meet stringent requirements for film thickness, uniformity, and adhesion, effectively preventing metal diffusion and ensuring electrical performance, structural integrity, and process compatibility.

For annealing in TSV processing, NAURA's furnace systems provide precise temperature control and excellent process stability, resulting in uniform copper grain distribution, reduced resistivity, and enhanced TSV quality and performance.

NAURA's cleaning equipment supports the removal of sidewall polymers by combining water-soluble chemistries, ensuring clean via interiors in TSV processes. In 2.5D applications, the systems minimize copper corrosion and enhance chemical utilization, improving process efficiency and economic value.

With a full suite of core process equipment tailored to advanced packaging, NAURA remains customer-focused, committed to enabling innovation, driving industrial advancement, and creating boundless possibilities.

[1] AI's surging demand for computing and storage power requires massive memory bandwidth to ensure performance scalability.

[2] AI chip training and inference involve intensive data transfers between memory and processors. CoWoS technology stacks multiple chips in a highly integrated package, significantly improving inter-chip communication efficiency.

[3] 2.5D packaging is an advanced integration technology that enables vertical interconnects between different chips or chip regions by incorporating TSVs (Through-Silicon Vias) and RDLs (Redistribution Layers) on the wafer's backside.

[4] UV tapes are primarily used to block ultraviolet exposure, protecting sensitive devices and process steps to ensure precision and quality in semiconductor manufacturing.